module PRBS_Generator (
    input clk,                  // Clock input
    input rst,                  // Reset input
    output reg [8:0] prbs_out   // 9-bit PRBS output
);

    reg [8:0] shift_reg;        // 9-bit shift register
    wire feedback;

    // Feedback taps at bit 8 and 4 (LFSR: S8 ^ S4)
    assign feedback = shift_reg[8] ^ shift_reg[4];

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            shift_reg <= 9'b1;  // 初始化为非零状态
            prbs_out <= 9'b1;
        end else begin
            shift_reg <= {shift_reg[7:0], feedback};
            prbs_out <= {shift_reg[7:0], feedback}; // 输出当前生成的PRBS
        end
    end
endmodule
